TSMC and Synopsys partner on A14 node and AI chip design

Taiwan Semiconductor Manufacturing Company (TSMC) and Synopsys announced new design innovations on September 23, 2026, aimed at accelerating development for artificial intelligence, high-performance computing, and advanced packaging systems.

The collaboration includes certified electronic design automation (EDA) flows across digital and analog implementations for TSMC's A14 process technology. The companies are also deploying agentic AI workflows across analog, digital, and multi-die designs, including chiplet floorplan co-optimization for TSMC 3DFabric architectures.

For advanced packaging, Synopsys expanded support for integrated voltage regulators on TSMC CoWoS technology and continued joint development for co-packaged optics on TSMC COUPE. On process nodes, Synopsys reached tape-out and enablement milestones on TSMC's N2P and N3P technologies for PCIe 7.0, HBM4, 64G UCIe, and LPDDR6, alongside ongoing IP development across compact nodes from 6nm down to 3nm.